Schloss Schönbrunn
Schönbrunn Palace, Former Imperial Summer Residence - Photo by Christer van der Meeren
24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
The International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS’2021) provides a forum for exchanging ideas, discussing research results, and presenting practical applications in the areas of design, test, and diagnosis of microelectronic digital, analog, and mixed-signal circuits and systems. The 24th symposium will be hosted as an online event by TU Wien in Vienna, Austria.
The keynotes at DDECS'2021 will be given by
Prof. Kaushik Roy, Purdue University, US
and
Prof. Yiorgos Makris, The University of Texas at Dallas, US
and
Rob Aitken, Fellow & Director of Technology, ARM
organized by
Alberto Bosio, University of Lyon, France
In the recent years, Approximate Computing (AxC) has become a major field of research to improve both speed and energy consumption in embedded and high-performance systems. By relaxing the need for fully precise or completely deterministic operations, approximate computing substantially improves energy efficiency. Convolutional Neural Networks (CNNs) show inherent resilience to insignificant errors due to their iterative nature and learning process. Therefore, an intrinsic tolerance to inexact computation is evidenced, and using the approximate computing paradigm to improve power and delay characteristics is therefore relevant. Indeed, CNNs lend well with AxC techniques. However, whereas AxC is widely adopted for achieving energy efficiency, its use for safety-critical applications has been investigated by only few recent works. The non-trivial question that this special session intends to answer is “How introducing errors during computation can indeed lead to a more secure and reliable application?”. The session will thus present different applications of AxC to design and implement efficient, secure and reliable high computing demanding applications such as the case of Deep Learning.
organized by
Petr Fiser, Czech Technical University in Prague, Czech Republic
Not many years ago, logic synthesis seemed to be an already resolved topic, and it appeared that no significant progress could be made in this field anymore. However, things have changed when “emerging technologies” came to play. Novel technology nodes with their unique properties are inexorably being discovered every year, encouraging researchers to devise novel synthesis algorithms tailored to these technologies. Logic primitives like XOR or majority gates, which used to be prohibitive because of their size in CMOS, now become of increasing interest because of their efficient implementation in nanotechnologies. Memristors have been successfully manufactured in the recent past, bringing an entirely new view on logic synthesis. This special session is focused on logic synthesis and verification algorithms, intended especially (but not only) for such technologies.
Muhammad Shafique, NYU Abu Dhabi, UAE
Andreas Steininger, TU Wien, Austria
Goran Stojanović, University of Novi Sad, Serbia
Lukáš Sekanina, Brno University of Technology, Czech Republic
Miloš Krstić, IHP and University Potsdam, Germany
Vojtěch Mrázek, Brno University of Technology, Czech Republic
Adrijan Barić, University of Zagreb, Croatia
Matthias Függer, CNRS & LSV, ENS Paris-Saclay & Inria, France
Jie Han, University of Alberta, Canada
Mottaqiallah Taouil, TU Delft, Netherlands
Jürgen Maier, TU Wien, Austria
Traude Sommer, TU Wien, Austria
Florian Huemer, TU Wien, Austria
Florian Kriebel, TU Wien, Austria
Adrijan Baric, University of Zagreb, Croatia
Cristiana Bolchini, Politecnico di Milano, Italy
Alberto Bosio, University of Lyon, France
Luca Cassano, Politecnico di Milano, Italy
Maciej Ciesielski, Univ. of Massachusetts, USA
Gyorgy Cserey, Pazmany Peter Catholic University, Hungary
Mirjana Damnjanovic, University of Novi Sad, Serbia
Martin Danek, daiteq s.r.o., Czech Republic
Stanisław Deniziak, Kielce University of Technology, Poland
Manfred Dietrich, Dikuli Unternehmensberatung, Germany
Rolf Drechsler, University of Bremen/DFKI, Germany
Milos Drutarovsky, Technical University of Kosice, Slovakia
Peeter Ellervee, Tallinn University of Technology, Estonia
Marius Enachescu, University Politehnica Bucharest, Romania
Goerschwin Fey, TU Hamburg, Germany
Petr Fiser, Czech Technical University in Prague, Czech Republic
Matthias Fuegger, CNRS & LSV, ENS Paris-Saclay
Tomasz Garbolino, Silesian University of Technology, Poland
Patrick Girard, LIRMM/CNRS, France
Jie Han, University of Alberta, Canada
Sybille Hellebrand, Paderborn University, Germany
Katarina Jelemenska, FIIT STU Bratislava, Slovakia
Maksim Jenihhin, Tallinn University of Technology, Estonia
Dominik Kasprowicz, Warsaw University of Technology, Poland
Martin Keim, Mentor, A Siemens Business
Milos Krstic, IHP, Germany
Hana Kubatova, CTU in Prague, Czech Republic
Wieslaw Kuzmicz, Warsaw University of Technology, Poland
Erik Larsson, Lund University, Sweden
Gildas Leger, Universidad de Sevilla, Spain
Regis Leveugle, Grenoble INP, France
Dominik Macko, Slovak University of Technology, Slovakia
Paolo Maistri, TIMA, France
Hans Manhaeve, Ridgetop Europe, Belgium
Tetsuya Matsumura, Nihon University, Japan
Liviu-Cristian Miclea, Technical University of Cluj-Napoca, Romania
Farshad Moradi, Aarhus University, DK
Lukas Nagy, Slovak University of Technology, Slovakia
Ondrej Novak, TU Liberec, Czech Republic
Marco Ottavi, University of Rome Tor Vergata, Italy
Andras Pataricza, Budapest University of Technology and Economics, Hungary
Zebo Peng, Linkoping University, Sweden
Laurence Pierre, University Grenoble Alpes, France
Stanislaw J. Piestrak, University de Lorraine - Institut Jean Lamour, France
Witold Pleskacz, Warsaw University of Technology, Poland
Thomas Polzer, UAS Technikum Wien, Austria
Michele Portolan, INP Grenoble, France
Paolo Prinetto, Politecnico di Torino, Italy
Zbynek Raida, Brno University of Technology, Czech Republic
Jaan Raik, Tallinn University of Technology, Estonia
Bruno Rouzeyre, University Montpellier, France
Richard Ruzicka, Brno University of Technology, Czech Republic
Sebastian M. Sattler, Friedrich-Alexander-University Erlangen-Nuremberg, Germany
Mario Schölzel, University of Applied Science Nordhausen, Germany
Lukas Sekanina, Brno University of Technology, Czech Republic
Muhammad Shafique, NYU, UAE
Matteo Sonza Reorda, Politecnico di Torino, Italy
Janusz Sosnowski, Warsaw University of Technology, Poland
Zoran Stamenkovic, IHP - Leibniz-Institut für Innovative Mikroelektronik, Germany
Andreas Steininger, Vienna University of Technology, Austria
Goran Stojanovic, University of Novi Sad, Serbia
Viera Stopjakova, Slovak University of Technology, Slovakia
Ondrej Subrt, ASICentrum, Czech Republic
Kalle Tammemae, Tallinn University of Technology, Estonia
Mottaqiallah Taouil, Delft University of Technology, Netherlands
Paulo Teixeira, INESC.ID Lisboa, Portugal
Raimund Ubar, Tallinn University of Technology, Estonia
Mihai Udrescu, University Politehnica of Timisoara, Romania
Markus Ulbricht, IHP, Germany
Elena Ioana Vatajelu, TIMA/CNRS de Grenoble-Alpes, France
Diego Vazquez, Instituto de Microelectr¢nica de Sevilla / Universidad de Sevilla, Spain
Federico Venini, Xilinx, USA
Arnaud Virazel, LIRMM, France
Robert Wille, Johannes Kepler University Linz, Austria
Hans-Joachim Wunderlich, University of Stuttgart, Germany
Mustafa Berke Yelten, Istanbul Technical University, Turkey
Yervant Zorian, Synopsys, USA
DDECS’2021 provides a forum for exchanging ideas, discussing research results, and presenting practical applications in the areas of design, test, and diagnosis of microelectronic digital, analog, and mixed-signal circuits and systems. The topics include the following but are not limited to:
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You may now submit a contribution for DDECS'2021. Please select a type of contribution. Remember to click the "Complete Submission" button on the second screen! Accepted papers will be included in the Symposium Proceedings. Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements.
A paper presenting an original and novel scientific content (maximum 6 pages in the IEEE two-column format).
The paper is submitted from an industrial sector, possibly as a joint work with research institutes and it has the character of industrial results, e.g. a real chip design, fabrication defects analysis, a new design and/or test technique used in company, design and/or test problems that need to be solved, etc. The paper should have at most 6 pages in the IEEE two-column format.
A paper presenting results of a student's PhD or master work. In order to be eligible as a student paper, the first author has to be the student (or more than one student in case of joint work), and the second author the advisor. The accepted paper has to be presented by the student. The paper should have at most 4 pages in the IEEE two-column format.
Accepted tutorials will be embedded into the program. Authors should submit their proposal in the form of an extended abstract together with a short CV (max. 3 pages).
A paper presenting a new research in progress, evolving ideas, novel research directions, and/or experimental research, early results. The paper should have at most 4 pages in the IEEE two-column format. The accepted papers will not be included in IEEE Xplore.
All papers for DDECS'2021 must be submitted in English and use the two-column format template for conferences provided by the IEEE (link).
Each paper submitted to a special session has to be a Regular Paper. Please add a short comment “This paper is submitted to Special Session on [special_session_title]” to the “Remarks on This Contribution” field on the submission page.
Student grants will be available. Details about how to apply will be available soon.
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Paper Submission | |
Notification of Acceptance | March 21, 2021 |
Publication Ready Version Submission | TBA ... |
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