24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
The International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS’2021) provides a forum for exchanging ideas, discussing research results, and presenting practical applications in the areas of design, test, and diagnosis of microelectronic digital, analog, and mixed-signal circuits and systems. The 24th symposium will be hosted as an online event by TU Wien in Vienna, Austria.
We are pleased to announce that the keynotes at DDECS'2021 will be given by Prof. Kaushik Roy (Purdue University, US), Prof. Yiorgos Makris (UT Dallas, US) and Rob Aitken (Fellow & Director of Technology, ARM).
Abstract - Advances in machine learning, notably deep learning, have led to computers matching or surpassing human performance in several cognitive tasks including vision, speech and natural language processing. However, implementation of such neural algorithms in conventional "von-Neumann" architectures are several orders of magnitude more area and power expensive than the biological brain. Hence, we need fundamentally new approaches to sustain exponential growth in performance at high energy-efficiency beyond the end of the CMOS roadmap in the era of ‘data deluge’ and emergent data-centric applications. Exploring the new paradigm of computing necessitates a multi-disciplinary approach: exploration of new learning algorithms inspired from neuroscientific principles, developing network architectures best suited for such algorithms, new hardware techniques to achieve orders of improvement in energy consumption, and nanoscale devices that can closely mimic the neuronal and synaptic operations of the brain leading to a better match between the hardware substrate and the model of computation. In this talk, I will focus on our recent works on neuromorphic computing with spike based learning and the design of underlying hardware that can lead to quantum improvements in energy efficiency with good accuracy.
Speaker Biography - Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. He also the director of the center for brain-inspired computing (C-BRIC) funded by SRC/DARPA. His research interests include neuromorphic and emerging computing models, neuro-mimetic devices, spintronics, device-circuit-algorithm co-design for nano-scale Silicon and non-Silicon technologies, and low-power electronics. Dr. Roy has published more than 700 papers in refereed journals and conferences, holds 25 patents, supervised 90 PhD dissertations, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award (Charles Desoer Award), Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, DoD Vannevar Bush Faculty Fellow (2014-2019), Semiconductor Research Corporation Aristotle award in 2015, and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay) and Global Foundries visiting Chair at National University of Singapore. He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.
Abstract - While many applications of machine learning in various semiconductor manufacturing and test tasks have been heavily researched over the last two decades, few have actually seen the light of day in a real production environment. Recently, the popularity of contemporary artificial intelligence methods, such as deep learning, has reignited the enthusiasm and reinvigorated the discussion regarding the potential of statistical and machine learning-based solutions toward reducing test cost, increasing test quality, improving yield and test floor logistics, as well as providing guidance to designers and process engineers alike. In this presentation, I will discuss the lessons we have learned during 15 years of interactions between academia and industry in developing machine learning-based semiconductor manufacturing and test solutions and I will review the key challenges that we have encountered both in demonstrating and in transitioning such solutions from a research to a production environment. Organized around various fallacies that are prevalent in the community regarding the application of traditional or contemporary machine learning methods in this context, as well as the pitfalls that have given rise to these fallacies, the ultimate intention of this presentation is to draw attention to the true operational challenges involved and to suggest efforts which can enable and expedite industrial deployment.
Speaker Biography - Yiorgos Makris received the Diploma of Computer Engineering from the University of Patras, Greece, in 1995 and the M.S. and Ph.D. degrees in Computer Engineering from the University of California, San Diego, in 1998 and 2001, respectively. After spending a decade on the faculty of Yale University, he joined UT Dallas where he is now a Professor of Electrical and Computer Engineering, the Co-Founder and Site-PI of the NSF Industry University Cooperative Research Center on Hardware and Embedded System Security and Trust (NSF CHEST I/UCRC), as well as the Leader of the Safety, Security and Healthcare Thrust of the Texas Analog Center of Excellence (TxACE) and the Director of the Trusted and RELiable Architectures (TRELA) Research Laboratory. His research focuses on applications of machine learning and statistical analysis in the development of trusted and reliable integrated circuits and systems, with particular emphasis in the analog/RF domain. He serves as an Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and has served as an Associate Editor for the IEEE Information Forensics and Security and the IEEE Design & Test of Computers Periodical, as a guest editor for the IEEE Transactions on Computers and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He also served as the 2016-2017 general chair and the 2013-2014 program chair of the IEEE VLSI Test Symposium. He is a recipient of the 2006 Sheffield Distinguished Teaching Award, Best Paper Awards from the 2013 IEEE/ACM Design Automation and Test in Europe (DATE'13) conference and the 2015 IEEE VLSI Test Symposium (VTS'15), as well as Best Hardware Demonstration Awards from the 2016 and the 2018 IEEE Hardware-Oriented Security and Trust Symposia (HOST'16 and HOST'18) and a recipient of the 2020 Faculty Research Award from the Erik Jonsson School of Engineering and Computer Science at UT Dallas.
Abstract - After a half century of CMOS, designers understand the inherent tradeoffs between dependability and resilience on one hand and performance, power and area on the other. As Moore’s law slows down, new devices and technologies are being proposed as alternatives to CMOS in both logic and memory design, and many of these have inherent dependability challenges. This talk looks at existing approaches in light of these new challenges and discusses possible ways forward.
Speaker Biography - Rob Aitken is an Arm Fellow and Director of Technology for Arm Research. His responsibilities include developing Arm’s research agenda, including identifying disruptive technologies, monitoring the global technology landscape, and coordinating research efforts within and outside of Arm. His research interests include emerging technologies, memory design, design for variability, resilient computing, and statistical design. He has published over 100 technical papers on a wide range of topics and holds over 40 US patents. Dr. Aitken joined Arm as part of its acquisition of Artisan Components in 2004. He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow.
organized by
Alberto Bosio, University of Lyon, France
In the recent years, Approximate Computing (AxC) has become a major field of research to improve both speed and energy consumption in embedded and high-performance systems. By relaxing the need for fully precise or completely deterministic operations, approximate computing substantially improves energy efficiency. Convolutional Neural Networks (CNNs) show inherent resilience to insignificant errors due to their iterative nature and learning process. Therefore, an intrinsic tolerance to inexact computation is evidenced, and using the approximate computing paradigm to improve power and delay characteristics is therefore relevant. Indeed, CNNs lend well with AxC techniques. However, whereas AxC is widely adopted for achieving energy efficiency, its use for safety-critical applications has been investigated by only few recent works. The non-trivial question that this special session intends to answer is “How introducing errors during computation can indeed lead to a more secure and reliable application?”. The session will thus present different applications of AxC to design and implement efficient, secure and reliable high computing demanding applications such as the case of Deep Learning.
organized by
Petr Fiser, Czech Technical University in Prague, Czech Republic
Not many years ago, logic synthesis seemed to be an already resolved topic, and it appeared that no significant progress could be made in this field anymore. However, things have changed when “emerging technologies” came to play. Novel technology nodes with their unique properties are inexorably being discovered every year, encouraging researchers to devise novel synthesis algorithms tailored to these technologies. Logic primitives like XOR or majority gates, which used to be prohibitive because of their size in CMOS, now become of increasing interest because of their efficient implementation in nanotechnologies. Memristors have been successfully manufactured in the recent past, bringing an entirely new view on logic synthesis. This special session is focused on logic synthesis and verification algorithms, intended especially (but not only) for such technologies.
Muhammad Shafique, NYU Abu Dhabi, UAE
Andreas Steininger, TU Wien, Austria
Goran Stojanović, University of Novi Sad, Serbia
Lukáš Sekanina, Brno University of Technology, Czech Republic
Miloš Krstić, IHP and University Potsdam, Germany
Vojtěch Mrázek, Brno University of Technology, Czech Republic
Adrijan Barić, University of Zagreb, Croatia
Matthias Függer, CNRS & LSV, ENS Paris-Saclay & Inria, France
Jie Han, University of Alberta, Canada
Mottaqiallah Taouil, TU Delft, Netherlands
Jürgen Maier, TU Wien, Austria
Traude Sommer, TU Wien, Austria
Florian Huemer, TU Wien, Austria
Florian Kriebel, TU Wien, Austria
Adrijan Baric, University of Zagreb, Croatia
Cristiana Bolchini, Politecnico di Milano, Italy
Alberto Bosio, University of Lyon, France
Luca Cassano, Politecnico di Milano, Italy
Maciej Ciesielski, Univ. of Massachusetts, USA
Gyorgy Cserey, Pazmany Peter Catholic University, Hungary
Mirjana Damnjanovic, University of Novi Sad, Serbia
Martin Danek, daiteq s.r.o., Czech Republic
Stanisław Deniziak, Kielce University of Technology, Poland
Manfred Dietrich, Dikuli Unternehmensberatung, Germany
Rolf Drechsler, University of Bremen/DFKI, Germany
Milos Drutarovsky, Technical University of Kosice, Slovakia
Peeter Ellervee, Tallinn University of Technology, Estonia
Marius Enachescu, University Politehnica Bucharest, Romania
Goerschwin Fey, TU Hamburg, Germany
Petr Fiser, Czech Technical University in Prague, Czech Republic
Matthias Fuegger, CNRS & LSV, ENS Paris-Saclay
Tomasz Garbolino, Silesian University of Technology, Poland
Patrick Girard, LIRMM/CNRS, France
Jie Han, University of Alberta, Canada
Sybille Hellebrand, Paderborn University, Germany
Katarina Jelemenska, FIIT STU Bratislava, Slovakia
Maksim Jenihhin, Tallinn University of Technology, Estonia
Dominik Kasprowicz, Warsaw University of Technology, Poland
Martin Keim, Mentor, A Siemens Business
Milos Krstic, IHP, Germany
Hana Kubatova, CTU in Prague, Czech Republic
Wieslaw Kuzmicz, Warsaw University of Technology, Poland
Erik Larsson, Lund University, Sweden
Gildas Leger, Universidad de Sevilla, Spain
Regis Leveugle, Grenoble INP, France
Dominik Macko, Slovak University of Technology, Slovakia
Paolo Maistri, TIMA, France
Hans Manhaeve, Ridgetop Europe, Belgium
Tetsuya Matsumura, Nihon University, Japan
Liviu-Cristian Miclea, Technical University of Cluj-Napoca, Romania
Farshad Moradi, Aarhus University, DK
Lukas Nagy, Slovak University of Technology, Slovakia
Ondrej Novak, TU Liberec, Czech Republic
Marco Ottavi, University of Rome Tor Vergata, Italy
Andras Pataricza, Budapest University of Technology and Economics, Hungary
Zebo Peng, Linkoping University, Sweden
Laurence Pierre, University Grenoble Alpes, France
Stanislaw J. Piestrak, University de Lorraine - Institut Jean Lamour, France
Witold Pleskacz, Warsaw University of Technology, Poland
Thomas Polzer, UAS Technikum Wien, Austria
Michele Portolan, INP Grenoble, France
Paolo Prinetto, Politecnico di Torino, Italy
Zbynek Raida, Brno University of Technology, Czech Republic
Jaan Raik, Tallinn University of Technology, Estonia
Bruno Rouzeyre, University Montpellier, France
Richard Ruzicka, Brno University of Technology, Czech Republic
Sebastian M. Sattler, Friedrich-Alexander-University Erlangen-Nuremberg, Germany
Mario Schölzel, University of Applied Science Nordhausen, Germany
Lukas Sekanina, Brno University of Technology, Czech Republic
Muhammad Shafique, NYU, UAE
Matteo Sonza Reorda, Politecnico di Torino, Italy
Janusz Sosnowski, Warsaw University of Technology, Poland
Zoran Stamenkovic, IHP - Leibniz-Institut für Innovative Mikroelektronik, Germany
Andreas Steininger, Vienna University of Technology, Austria
Goran Stojanovic, University of Novi Sad, Serbia
Viera Stopjakova, Slovak University of Technology, Slovakia
Ondrej Subrt, ASICentrum, Czech Republic
Kalle Tammemae, Tallinn University of Technology, Estonia
Mottaqiallah Taouil, Delft University of Technology, Netherlands
Paulo Teixeira, INESC.ID Lisboa, Portugal
Raimund Ubar, Tallinn University of Technology, Estonia
Mihai Udrescu, University Politehnica of Timisoara, Romania
Markus Ulbricht, IHP, Germany
Elena Ioana Vatajelu, TIMA/CNRS de Grenoble-Alpes, France
Diego Vazquez, Instituto de Microelectr¢nica de Sevilla / Universidad de Sevilla, Spain
Federico Venini, Xilinx, USA
Arnaud Virazel, LIRMM, France
Robert Wille, Johannes Kepler University Linz, Austria
Hans-Joachim Wunderlich, University of Stuttgart, Germany
Mustafa Berke Yelten, Istanbul Technical University, Turkey
Yervant Zorian, Synopsys, USA
DDECS’2021 provides a forum for exchanging ideas, discussing research results, and presenting practical applications in the areas of design, test, and diagnosis of microelectronic digital, analog, and mixed-signal circuits and systems. The topics include the following but are not limited to:
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You may now submit a contribution for DDECS'2021. Please select a type of contribution. Remember to click the "Complete Submission" button on the second screen! Accepted papers will be included in the Symposium Proceedings. Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements.
A paper presenting an original and novel scientific content (maximum 6 pages in the IEEE two-column format).
The paper is submitted from an industrial sector, possibly as a joint work with research institutes and it has the character of industrial results, e.g. a real chip design, fabrication defects analysis, a new design and/or test technique used in company, design and/or test problems that need to be solved, etc. The paper should have at most 6 pages in the IEEE two-column format.
A paper presenting results of a student's PhD or master work. In order to be eligible as a student paper, the first author has to be the student (or more than one student in case of joint work), and the second author the advisor. The accepted paper has to be presented by the student. The paper should have at most 4 pages in the IEEE two-column format.
Accepted tutorials will be embedded into the program. Authors should submit their proposal in the form of an extended abstract together with a short CV (max. 3 pages).
A paper presenting a new research in progress, evolving ideas, novel research directions, and/or experimental research, early results. The paper should have at most 4 pages in the IEEE two-column format. The accepted papers will not be included in IEEE Xplore.
All papers for DDECS'2021 must be submitted in English and use the two-column format template for conferences provided by the IEEE (link).
Each paper submitted to a special session has to be a Regular Paper. Please add a short comment “This paper is submitted to Special Session on [special_session_title]” to the “Remarks on This Contribution” field on the submission page.
Student grants will be available. Details about how to apply will be available soon.
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Paper Submission | |
Notification of Acceptance | March 21, 2021 |
Publication Ready Version Submission | TBA ... |
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